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A Study of Phase-Adjusting Architectures for Low-Phase-Noise Quadrature Voltage-Controlled Oscillators

  • Published:2023-02-01 Issue:2 Volume:E106.C Page:59-66
  • ISSN:0916-8524
  • Container-title:IEICE Transactions on Electronics
  • language:en
  • Short-container-title:IEICE Trans. Electron.

Author:

UGAJIN Mamoru1,KAKEI Yuya2,ITOH Nobuyuki3

Affiliation:

1. Nippon Institute of Technology

2. Saizeriya Co., Ltd.

3. Okayama Prefectural University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Reference36 articles.

1. [1] C.E. Shannon, “A mathematical theory of communication,” The Bell System Technical Journal, vol.27, no.3, pp.379-423, 1948 (DOI: 10.1002/j.1538-7305.1948.tb01338.x). 10.1002/j.1538-7305.1948.tb01338.x

2. [2] A. Mazzanti, M. Sosio, M.M. Repossi, and F. Svelto, “A 24GHz sub-harmonic receiver front-end with integrated multi-phase LO generation in 65nm CMOS,” ISSCC Dig. Tech. Papers, 216, 2008 (DOI: 10.1109/ISSCC.2008.4523134). 10.1109/isscc.2008.4523134

3. [3] K. Okada, K. Kondou, M. Miyahara, M. Shinagawa, H. Asada, R. Minami, T. Yamaguchi, A. Musa, Y. Tsukui, Y. Asakura, S.Tamonoki, H. Yamagishi, Y. Hino, T. Sato, H. Sakaguchi, N.Shimasaki, T. Ito, Y. Takeuchi, N. Li, Q. Bu, R. Murakami, K.Bunsen, K. Matsushita, M. Noda, and A. Matsuzawa, “Full four-channel 6.3-Gb/s 60-GHzCMOS transceiver with low-power analog and digital baseband circuitry,” IEEE J. Solid-State Circuits, vol.48, no.1, pp.46-65, 2013 (DOI: 10.1109/JSSC.2012.2218066). 10.1109/jssc.2012.2218066

4. [4] S. Ek, T. Påhlsson, A. Carlsson, A. Axholt, A.-K. Stenman, and H. Sjöland, “A 16-20 GHz LO system with 115 fs jitter for 24-30 GHz 5G in 28 nm FD-SOI CMOS,” 43rd IEEE European Solid State Circuits Conference, 110, 2017 (DOI: 10.1109/ESSCIRC.2017.8094573). 10.1109/esscirc.2017.8094573

5. [5] N. Xi, F. Lin, and T. Ye, “A low phase noise, high phase accuracy quadrature LC-VCO with dual-tail current biasing to insert reconfigurable phase delay,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.67, no.3, pp.450-454, 2020 (DOI: 10.1109/TCSII.2019.2923235). 10.1109/tcsii.2019.2923235
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