A 16–20 GHz LO system with 115 fs jitter for 24–30 GHz 5G in 28 nm FD-SOI CMOS-Reference-Cited by-同舟云学术

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A 16–20 GHz LO system with 115 fs jitter for 24–30 GHz 5G in 28 nm FD-SOI CMOS

Published:2017-09 Issue: Volume: Page:
ISSN:
Container-title:ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference
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Author:

Ek Staffan,Pahlsson Tony,Carlsson Anders,Axholt Andreas,Stenman Anna-Karin,Sjoland Henrik

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8061155/8094509/08094573.pdf?arnumber=8094573

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Study of Phase-Adjusting Architectures for Low-Phase-Noise Quadrature Voltage-Controlled Oscillators;IEICE Transactions on Electronics;2023-02-01

2. A quadrature voltage-controlled oscillator using phase-adjusting architecture for suppressing phase noise;IEICE Electronics Express;2021-05-25

3. A Fast Settling Fractional-$N$ DPLL With Loop-Order Switching;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2020-03

4. Performance, Power, and Area Design Trade-Offs in Millimeter-Wave Transmitter Beamforming Architectures;IEEE Circuits and Systems Magazine;2019

5. A 28-nm FD-SOI 115-fs Jitter PLL-Based LO System for 24–30-GHz Sliding-IF 5G Transceivers;IEEE Journal of Solid-State Circuits;2018-07

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