A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/8811631/08770261.pdf?arnumber=8770261
Cited by 16 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 10b 400MS/s 2x-Time-Interleaved 2-Then-1b/Cycle SAR ADC in 90nm CMOS;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. 10.8 A 281GHz, −1.5dBm Output-Power CMOS Signal Source Adopting a 46fsrms Jitter D-Band Cascaded Subharmonically Injection-Locked Sub-Sampling PLL with a 274MHz Reference;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18
3. Artificial Neural Network Based Calibration for a 12 b 250 MS/s Pipelined-SAR ADC With Ring Amplifier in 40-nm CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2024
4. An 11bit 360MS/s Pipelined SAR ADC with Dynamic Negative-C Assisted Residue Amplifier;2023 IEEE Asian Solid-State Circuits Conference (A-SSCC);2023-11-05
5. A 400-MS/s 12-bit Voltage-Time Hybrid ADC with a Ping-Pong SAR TDC for Speed Enhancement;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
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