10.8 A 281GHz, −1.5dBm Output-Power CMOS Signal Source Adopting a 46fs<sub>rms</sub> Jitter D-Band Cascaded Subharmonically Injection-Locked Sub-Sampling PLL with a 274MHz Reference-Reference-Cited by-同舟云学术

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10.8 A 281GHz, −1.5dBm Output-Power CMOS Signal Source Adopting a 46fs_rms Jitter D-Band Cascaded Subharmonically Injection-Locked Sub-Sampling PLL with a 274MHz Reference

Published:2024-02-18 Issue: Volume: Page:202-204
ISSN:
Container-title:2024 IEEE International Solid-State Circuits Conference (ISSCC)
language:
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Author:

Moon Byeong-Taek¹,Park Hyun-Chul²,Lee Sang-Gug¹

Affiliation:

1. Korea Advanced Institute of Science and Technology,Daejeon,Korea

2. Samsung Electronics,Hwaseong,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10454133/10454267/10454484.pdf?arnumber=10454484

Reference6 articles.

1. A 300GHz 52mW CMOS Receiver with On-Chip LO Generation

2. A 270-Ghz Fully-Integrated Frequency Synthesizer in 65nm CMOS

3. A Low-Jitter and Low-Reference-Spur 320 GHz Signal Source With an 80 GHz Integer-N Phase-Locked Loop Using a Quadrature XOR Technique

4. 24.2 A 264-to-287GHz, −2.5dBm Output Power, and −92dBc/Hz 1MHz-Phase-Noise CMOS Signal Source Adopting a 75fs_rms Jitter D-Band Cascaded Sub-Sampling PLL

5. 23.4 An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector in 65nm CMOS

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