24.2 A 264-to-287GHz, −2.5dBm Output Power, and −92dBc/Hz 1MHz-Phase-Noise CMOS Signal Source Adopting a 75fs<sub>rms</sub> Jitter D-Band Cascaded Sub-Sampling PLL-Reference-Cited by-同舟云学术

24.2 A 264-to-287GHz, −2.5dBm Output Power, and −92dBc/Hz 1MHz-Phase-Noise CMOS Signal Source Adopting a 75fs_rms Jitter D-Band Cascaded Sub-Sampling PLL

Published:2023-02-19 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Solid- State Circuits Conference (ISSCC)
language:
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Author:

Moon Byeong-Taek¹,Lee Sang-Gug¹,Choi Jaehyouk¹

Affiliation:

1. Korea Advanced Institute of Science and Technology,Daejeon,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067713.pdf?arnumber=10067713

Reference7 articles.

1. An and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector in 65nm CMOS;yoo;ISSCC,2021

2. A Low-Jitter and Low-Reference-Spur 320 GHz Signal Source With an 80 GHz Integer-N Phase-Locked Loop Using a Quadrature XOR Technique

3. A 270-Ghz Fully-Integrated Frequency Synthesizer in 65nm CMOS

4. A 237–263 GHz CMOS Frequency Doubler with 0.9 dBm Output Power and 2.87 % Power Efficiency Based on Harmonic Matched $G_{\max}$-Core

5. A High-Gain mm-Wave Amplifier Design: An Analytical Approach to Power Gain Boosting;bameri;IEEE JSSC,2017

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1. 10.8 A 281GHz, −1.5dBm Output-Power CMOS Signal Source Adopting a 46fs_rms Jitter D-Band Cascaded Subharmonically Injection-Locked Sub-Sampling PLL with a 274MHz Reference;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

2. A High-Efficiency High-Power 170-176-GHz Frequency Stabilized Quadrature Radiator;IEEE Journal of Solid-State Circuits;2024-01