A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy-Reference-Cited by-同舟云学术

登录注册会员服务联系我们

A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy

Published:2013-06 Issue:6 Volume:48 Page:1398-1415
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Hyung-Joon Jeon ,Kulkarni R.,Yung-Chung Lo ,Jusung Kim ,Silva-Martinez J.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/6518166/06509992.pdf?arnumber=6509992

Cited by 30 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 20-Gb/s Jitter-Tolerance-Enhanced Baud-Rate CDR Circuitwith One-Tap DFE;2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA);2024-04-22

2. A 270 fJ/op 5.8 GHz MOS Current Mode Logic D-Latch for High-Speed Application;2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2023-06-18

3. A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation;International Journal of Circuit Theory and Applications;2023-01-04

4. A 12.93–16 Gb/s Reference-Less Baud-Rate CDR Circuit With One-Tap DFE and Semirotational Frequency Detection;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023

5. A 1.45-pJ/b 16-Gb/s Edge-Based Sub-Baud-Rate Digital CDR Circuit;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-12

同舟云学术

1.学者识别学者识别

2.学术分析学术分析

3.人才评估人才评估

"同舟云学术"是以全球学者为主线，采集、加工和组织学术论文而形成的新型学术文献查询和分析系统，可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容，当前同舟云学术共收录了国内外主流学术期刊6万余种，收集的期刊论文及会议论文总量共计约1.5亿篇，并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询！咨询电话：010-8811{复制后删除}0370

www.globalauthorid.com

TOP