A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET-Reference-Cited by-同舟云学术

A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET

Published:2020-04 Issue:4 Volume:55 Page:1108-1123
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Tajalli Armin^ORCID,Bastani Parizi Mani^ORCID,Carnelli Dario Albino,Cao Chen,Gharibdoust Kiarash^ORCID,Gorret Davide,Gupta Amit,Hall Christopher,Hassanin Ahmed,Hofstra Klaas L.,Holden Brian,Hormati Ali,Keay John,Mogentale Yohann,Perrin Victor,Phillips John,Raparthy Sumathi,Shokrollahi Amin,Stauffer David^ORCID,Simpson Richard,Stewart Andrew,Surace Giuseppe,Talebi Amiri Omid,Truffa Emanuele,Tschank Anton,Ulrich Roger,Walter Christoph,Singh Anant

Funder

Kandou Bus

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9048008/08957252.pdf?arnumber=8957252

Cited by 26 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. DMT 3L4W: A 3-Lane 4-Wire Signaling With Discrete Multitone Modulation for High-Speed Wireline Chip-to-Chip Interconnects;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR;IEEE Journal of Solid-State Circuits;2024-02

3. A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization;IEEE Journal of Solid-State Circuits;2024-01

4. A 2 x 24Gb/s Single-Ended Transceiver with Channel-Independent Encoder-Based Crosstalk Cancellation in 28nm CMOS;2023 IEEE Asian Solid-State Circuits Conference (A-SSCC);2023-11-05

5. A 20-Gb/s/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links;IEEE Journal of Solid-State Circuits;2023-11