A 20-Gb/s/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links-Reference-Cited by-同舟云学术

A 20-Gb/s/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links

Published:2023-11 Issue:11 Volume:58 Page:3253-3265
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Seo Jaeyoung¹^ORCID,Lee Sooeun¹^ORCID,Lee Myungguk²^ORCID,Moon Changjae²,Kim Byungsub³^ORCID

Affiliation:

1. Samsung Electronics, Hwaseong, South Korea

2. Department of Electrical Engineering, Pohang University of Science and Technology, Pohang, South Korea

3. Department of Electrical Engineering, Department of Convergence IT EngineeringDepartment of Semiconductor EngineeringGraduate School of Artificial Intelligence, Pohang University of Science and Technology, Pohang-si, South Korea

Funder

Commercializations Promotion Agency Outcomes (COMPA) funded by the Ministry of Science and ICT (MSIT), Korea Government

Institute of Information & Communications Technology Planning & Evaluation (IITP) funded by the Korea government (MSIT)

Samsung Electronics Co., Ltd

BK21 FOUR project of National Research Foundation (NRF) for the Department of Electrical Engineering, POSTECH

National R&D Program through the NRF of Korea funded by the Korea Government

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10292770/10171209.pdf?arnumber=10171209

Reference29 articles.

1. A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications

2. A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS

3. A 20-Gb/s/pin 0.0024-mm² Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error and RX Supply Noise for DCC/CDR-less Short-Reach Memory Interfaces

4. Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links—A Tutorial

5. A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits

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