An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114-Reference-Cited by-同舟云学术

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An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114

Published:2019-04 Issue:4 Volume:54 Page:927-936
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Choi Seojin^ORCID,Yoo Seyeon^ORCID,Lee Yongsun^ORCID,Jo Yongwoo^ORCID,Lee Jeonghyun^ORCID,Lim Younghyun^ORCID,Choi Jaehyouk^ORCID

Funder

Samsung

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/8674728/08581591.pdf?arnumber=8581591

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Wide Tuning Range 4-Stage Ring VCO for Phase Locked Loop;2023 First International Conference on Microwave, Antenna and Communication (MAC);2023-03-24

2. A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68;IEEE Journal of Solid-State Circuits;2023-01

3. Phase Noise Analysis of Periodically ON/OFF Switched Oscillators;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-01

4. Injection-Locking Techniques for CMOS Millimeter-Wave and Terahertz Signal Generation;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-07

5. A Wide-Lock-In-Range and Low-Jitter 12–14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop;IEEE Journal of Solid-State Circuits;2022-02

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