A 600 µA 32 kHz Input 960 MHz Output CP-PLL With 530 ps Integrated Jitter in 28 nm FD-SOI Process-Reference-Cited by-同舟云学术

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A 600 µA 32 kHz Input 960 MHz Output CP-PLL With 530 ps Integrated Jitter in 28 nm FD-SOI Process

Published:2015-07 Issue:7 Volume:50 Page:1680-1689
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Lahiri Abhirup,Gupta Nitin,Kumar Anand,Dhadda Pradeep

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/7131594/07091963.pdf?arnumber=7091963

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Fractional-N PLL for Multi-phase Clock Generation with Loop Bandwidth Enhancement;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. A ULP Long-Range Active-RF Tag With Automatically Calibrated Antenna–TRX Interface;IEEE Journal of Solid-State Circuits;2024

3. A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth;IEEE Journal of Solid-State Circuits;2021-12

4. Evaluation of a Filter-less AD-PLL with a Wide Input Frequency Range Using a Fast-Locking Algorithm;2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS);2021-11-28

5. 32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth;2021 IEEE International Solid- State Circuits Conference (ISSCC);2021-02-13

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