Evaluation of a Filter-less AD-PLL with a Wide Input Frequency Range Using a Fast-Locking Algorithm-Reference-Cited by-同舟云学术

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Evaluation of a Filter-less AD-PLL with a Wide Input Frequency Range Using a Fast-Locking Algorithm

Published:2021-11-28 Issue: Volume: Page:
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Container-title:2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)
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Author:

Robles Roberto Andrino,Harada Tomochika,Yokoyama Michio

Funder

University of Tokyo

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9665417/9665446/09665560.pdf?arnumber=9665560

Reference6 articles.

1. All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply

2. Ultra-low power and dependability for IoT devices (Invited paper for IoT technologies)

3. A Low-Power and High-Frequency Phase Frequency Detector for a 3.33-GHz Delay Locked Loop

4. A 600 µA 32 kHz Input 960 MHz Output CP-PLL With 530 ps Integrated Jitter in 28 nm FD-SOI Process

5. A Low Power 0.6V Filter-less AD-PLL with a Fast Locking Algorithm in the Subthreshold Region;andrino;Int Symp Intelligent Signal Processing and Communication Systems,0

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 0.6V Beat-Frequency ADC with Processing of Oscillator Internal States for Resolution Improvement;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04

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