32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays-Reference-Cited by-同舟云学术

32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays

Published:2021-02-13 Issue: Volume: Page:
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Container-title:2021 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Santiccioli Alessio,Mercandelli Mario,Dartizio Simone M.,Tesolin Francesco,Karman Saleh,Shehata Abanob,Bertulessi Luca,Buccoleri Francesco,Avallone Luca,Parisi Angelo,Cherniak Dmytro,Lacaita Andrea L.,Kennedy Michael Peter,Samori Carlo,Levantino Salvatore

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9365732/9365735/09365972.pdf?arnumber=9365972

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2. A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays;IEEE Journal of Solid-State Circuits;2023-09

3. A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner;IEEE Journal of Solid-State Circuits;2023-03

4. A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time;IEEE Journal of Solid-State Circuits;2022-12

5. A Continuous K-Band Phase Shifter Based on Injection-Locked Dual Voltage-Controlled Oscillators;IEEE Microwave and Wireless Components Letters;2022-09