A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time
Author:
Affiliation:
1. Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy
2. Infineon Technologies AG, Villach, Austria
3. Dipartimento di Ingegneria dell’Informazione, University of Padua, Padua, Italy
Funder
Infineon Technologies, Villach
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/9962295/09907041.pdf?arnumber=9907041
Reference33 articles.
1. A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth
2. A 23-GHz Low-Phase-Noise Digital Bang–Bang PLL for Fast Triangular and Sawtooth Chirp Modulation
3. All-Digital PLL With Ultra Fast Settling
4. Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops
5. A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping
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5. A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays;IEEE Journal of Solid-State Circuits;2023-09
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