A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes-Reference-Cited by-同舟云学术

A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes

Published:2022-02-20 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Solid- State Circuits Conference (ISSCC)
language:
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Author:

Tu Fengbin¹,Wu Zihan¹,Wang Yiqi¹,Liang Ling²,Liu Liu²,Ding Yufei²,Liu Leibo¹,Wei Shaojun¹,Xie Yuan²,Yin Shouyi¹

Affiliation:

1. Tsinqhua University,Beijing,China

2. University of California,Santa Barbara,CA

Funder

NSFC

National Key R&D Program

Beijing Innovation Center for Future Chip

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731645.pdf?arnumber=9731645

Reference5 articles.

1. Big Bird: Transformers for Longer Sequences;zaheer;NeurIPS,2020

2. An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications;chih;ISSCC,2021

3. ETC: Encoding Long and Structured Inputs in Transformers

4. 16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

5. A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating;yue;ISSCC,2021

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