A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization-Reference-Cited by-同舟云学术

A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization

Published:2022-02-20 Issue: Volume: Page:
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Container-title:2022 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Park Myeong-Jae¹,Cho Ho Sung¹,Yun Tae-Sik¹,Byeon Sangjin¹,Koo Young Jun¹,Yoon Sangsic¹,Lee Dong Uk¹,Choi Seokwoo¹,Park Jihwan¹,Lee Jinhyung¹,Cho Kyungjun¹,Moon Junil¹,Yoon Byung-Kuk¹,Park Young-Jun¹,Oh Sang-muk¹,Lee Chang Kwon¹,Kim Tae-Kyun¹,Lee Seong-Hee¹,Kim Hyun-Woo¹,Ju Yucheon¹,Lim Seung-Kyun¹,Baek Seung Geun¹,Lee Kyo Yun¹,Lee Sang Hun¹,We Woo Sung¹,Kim Seungchan¹,Choi Yongseok¹,Lee Seong-Hak¹,Yang Seung Min¹,Lee Gunho¹,Kim In-Keun¹,Jeon Younghyun¹,Park Jae-Hyung¹,Yun Jong Chan¹,Park Chanhee¹,Kim Sun-Yeol¹,Kim Sungjin¹,Lee Dong-Yeol¹,Oh Su-Hyun¹,Hwang Taejin¹,Shin Junghyun¹,Lee Yunho¹,Kim Hyunsik¹,Lee Jaeseung¹,Hur Youngdo¹,Lee Sangkwon¹,Jang Jieun¹,Chun Junhyun¹,Cho Joohwan¹

Affiliation:

1. SK hynix,Icheon,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731562.pdf?arnumber=9731562

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4. 22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme

5. 22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST

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