31.8 A 0.4-to-0.95GHz Distributed N-Path Noise-Cancelling Ultra-Low-Power RX with Integrated Passives Achieving −85dBm/100kb/s Sensitivity, −41dB SIR and 174dB RX FoM in 22nm CMOS-Reference-Cited by-同舟云学术

31.8 A 0.4-to-0.95GHz Distributed N-Path Noise-Cancelling Ultra-Low-Power RX with Integrated Passives Achieving −85dBm/100kb/s Sensitivity, −41dB SIR and 174dB RX FoM in 22nm CMOS

Published:2023-02-19 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Bialek Hayden¹,Johnston Matthew¹,Natarajan Arun¹

Affiliation:

1. Oregon State University,Corvallis,OR,United States

Funder

NSF

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067338.pdf?arnumber=10067338

Reference12 articles.

1. 21.5 An Integrated 2.4GHz-91.5dBm-Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver Achieving 2?W at 100ms Latency;bishop;ISSCC,2021

2. Enhanced Interference Rejection Bluetooth Low-Energy Back-Channel Receiver With LO Frequency Hopping

3. An LPWAN Radio with a Reconfigurable Data/Duty-Cycled-Wake-Up Receiver

4. Implications of Passive Mixer Transparency for Impedance Matching and Noise Figure in Passive Mixer-First Receivers

5. A 2.5kb/s-103dBm-Sensitivity Dual-Chirp Modulated ULP Receiver Achieving-41dB SIR;moosavifar;ISSCC,2022

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1. A 0.77mW 1.84nJ/bit Phase Noise Canceling Receiver for QAM and OFDM and Cellular IoT;2024 IEEE Radio Frequency Integrated Circuits Symposium (RFIC);2024-06-16

2. A Near-Zero Power Reconfigurable and Robust Multiband RF Wake-Up Receiver Achieving −108dBm Sensitivity Operating from −40° C to 70° C;2024 IEEE/MTT-S International Microwave Symposium - IMS 2024;2024-06-16

3. A -104dBm-Sensitivity Receiver with Shared Wireless LO and Envelope-Tracking Mixer Achieving -46dB SIR;2024 IEEE Custom Integrated Circuits Conference (CICC);2024-04-21

4. An Interference-Resilient Bit-Level Duty-Cycled ULP Receiver Leveraging a Dual-Chirp Modulation;IEEE Journal of Solid-State Circuits;2024-02