Fault Tolerant Adders With Low Overheads For Smart Computing
Author:
Affiliation:
1. Deccan College of Engineering & Technology,ECE Department,Hyderabad,India
2. GITAM University,ECE Department GSOT,Hyderabad,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9716239/9716227/09716402.pdf?arnumber=9716402
Reference15 articles.
1. Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking
2. Concurrent fault detection and location with minimal overhead in Ling parallel prefix adders with a scheme for fault tolerant Ling prefix adders
3. Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder
4. Fault-tolerant ripple-carry binary adder using partial triple modular redundancy (PTMR)
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