Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking-Reference-Cited by-同舟云学术

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Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking

Published:2011-08 Issue:8 Volume:19 Page:1504-1507
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Ghosh Swaroop,Roy Kaushik

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/5961215/05491281.pdf?arnumber=5491281

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Fault Tolerant Adders With Low Overheads For Smart Computing;2022 4th International Conference on Smart Systems and Inventive Technology (ICSSIT);2022-01-20

3. Concurrent fault detection and location with minimal overhead in Ling parallel prefix adders with a scheme for fault tolerant Ling prefix adders;Microelectronics Reliability;2021-12

4. Qualitative and Quantitative Analysis of Parallel-Prefix Adders;Lecture Notes in Electrical Engineering;2020-08-29

5. Built-in self-repair structure for real-time fault recovery applications;Microelectronics Reliability;2020-08

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