I/sub DDQ/ testing of bridging faults in logic resources of reconfigurable field programmable gate arrays-Reference-Cited by-同舟云学术

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I/sub DDQ/ testing of bridging faults in logic resources of reconfigurable field programmable gate arrays

Published:1998 Issue:10 Volume:47 Page:1136-1152
ISSN:0018-9340
Container-title:IEEE Transactions on Computers
language:
Short-container-title:IEEE Trans. Comput.

Author:

Lan Zhao ,Walker D.M.H.,Lombardi F.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://xplorestaging.ieee.org/ielx4/12/15732/00729796.pdf?arnumber=729796

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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3. FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders;VLSI Design;2013-11-07

4. Single‐configuration fault detection in application‐dependent testing of field programmable gate array interconnects;IET Computers & Digital Techniques;2013-05

5. Design-specific path delay testing in lookup-table-based FPGAs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2006-05

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