A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop
Author:
Affiliation:
1. The State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences,Beijing,China
2. University of Macau,Macau,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10090225/10090247/10090393.pdf?arnumber=10090393
Reference15 articles.
1. A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS
2. A 3.65 mW 5 bit 2GS/s flash ADC with built-in reference voltage in 65nm CMOS process
3. A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS
4. An Integral Path Self-Calibration Scheme for a Dual-Loop PLL
5. Comparator with built-in reference voltage generation and split-ROM encoder for a high-speed flash ADC
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