A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/9361453/09214993.pdf?arnumber=9214993
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1. Complexity reduction in multilevel speculative DFEs with unconstrained receiver response;Microelectronics Journal;2023-08
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3. A low jitter 50 Gb/s PAM4 optical receiver in 130 nm SiGe BiCMOS;Microelectronics Journal;2023-06
4. PAM-4 Receiver With 1-Tap DFE Using Clocked Comparator Offset Instead of Threshold Voltages for Improved LSB BER Performance;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-05
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