DHTS: A Dynamic Hybrid Tiling Strategy for Optimizing Stencil Computation on GPUs-Reference-Cited by-同舟云学术

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DHTS: A Dynamic Hybrid Tiling Strategy for Optimizing Stencil Computation on GPUs

Published:2023-10 Issue:10 Volume:72 Page:2795-2807
ISSN:0018-9340
Container-title:IEEE Transactions on Computers
language:
Short-container-title:IEEE Trans. Comput.

Author:

Liu Song¹^ORCID,Zhang Zengyuan¹^ORCID,Wu Weiguo¹^ORCID

Affiliation:

1. School of Computer Science and Technology, Xi'an Jiaotong University, Shaanxi, China

Funder

National Natural Science Foundation of China

Natural Science Basic Research Program of Shaanxi

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://xplorestaging.ieee.org/ielx7/12/10243393/10109884.pdf?arnumber=10109884

Reference41 articles.

1. Hybrid hexagonal/classical tiling for GPUs;grosser;Proc IEEE/ACM 12th Int Symp Code Gener Optim,2014

2. AN5D: automated stencil framework for high-degree temporal blocking on GPUs

3. Hierarchical overlapped tiling

4. Exploiting reuse and vectorization in blocked stencil computations on CPUs and GPUs

5. The Relation Between Diamond Tiling and Hexagonal Tiling

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