Exploiting reuse and vectorization in blocked stencil computations on CPUs and GPUs

Author:

Zhao Tuowen1,Basu Protonu2,Williams Samuel3,Hall Mary1,Johansen Hans3

Affiliation:

1. University of Utah

2. Facebook

3. Lawrence Berkeley National Lab

Funder

U.S. Department of Energy

U.S. Department of Energy and National Nuclear Security Administration

Publisher

ACM

Reference46 articles.

1. 2016. High-Performance Geometric Multigrid. http://hpgmg.org 2016. High-Performance Geometric Multigrid. http://hpgmg.org

2. 3D Seismic Imaging through Reverse-Time Migration on Homogeneous and Heterogeneous Multi-Core Processors

3. Compiler-Directed Transformation for Higher-Order Stencils

4. PATUS: A Code Generation and Autotuning Framework for Parallel Iterative Stencil Computations on Modern Microarchitectures

5. Kaushik Datta. 2009. Auto-tuning Stencil Codes for Cache-Based Multicore Platforms. Ph.D. Dissertation. EECS Department University of California Berkeley. Kaushik Datta. 2009. Auto-tuning Stencil Codes for Cache-Based Multicore Platforms. Ph.D. Dissertation. EECS Department University of California Berkeley.

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