A Comprehensive Gate and Drain Trapping/Detrapping Noise Model and its Implications for Thin-Dielectric MOSFETs-Reference-Cited by-同舟云学术

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A Comprehensive Gate and Drain Trapping/Detrapping Noise Model and its Implications for Thin-Dielectric MOSFETs

Published:2021-10 Issue:10 Volume:68 Page:4826-4833
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Asanovski Ruben^ORCID,Palestri Pierpaolo^ORCID,Caruso Enrico^ORCID,Selmi Luca^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/9546692/09520089.pdf?arnumber=9520089

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Enhanced breakdown voltage for p-GaN gate AlGaN/GaN HEMT on AlN/Si with triple trenches: A simulation study;Results in Physics;2024-09

2. Simulation of Trap-Induced Noise Characteristics in 3-nm Complementary FET;2024 IEEE Silicon Nanoelectronics Workshop (SNW);2024-06-15

3. Deep Learning-Assisted Trap Extraction Method from Noise Power Spectral Density for MOSFETs;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14

4. Characterization and Advanced Modeling of Dielectric Defects in Low-Thermal Budget RMG MOSFETs Using 1/f Noise Analysis;IEEE Transactions on Electron Devices;2024-03

5. Simulation study of trap-induced noise characteristics in FDSOI MOSFETs;Japanese Journal of Applied Physics;2024-03-01

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