Defect-oriented dynamic fault models for embedded-SRAMs
Author:
Publisher
IEEE Comput. Soc
Link
http://xplorestaging.ieee.org/ielx5/8721/27596/01231664.pdf?arnumber=1231664
Cited by 21 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. SRAM Memory Testing Methods and Analysis;Advances in Systems Analysis, Software Engineering, and High Performance Computing;2023-12-18
2. Comparative Analysis of Open and Short Defects in Embedded SRAM Using Parasitic Extraction Method for Deep Submicron Technology;Wireless Personal Communications;2023-08-28
3. An Experimental Evaluation of Resistive Defects and Different Testing Solutions in Low-Power Back-Biased SRAM Cells;Electronics;2022-01-10
4. Analysis of Open Defect Faults in Single 6T SRAM Cell Using R and C Parasitic Extraction Method;2021 International Conference on Disruptive Technologies for Multi-Disciplinary Research and Applications (CENTCON);2021-11-19
5. Comparing different solutions for testing resistive defects in low-power SRAMs;2021 IEEE 22nd Latin American Test Symposium (LATS);2021-10-27
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