Fault Tolerant Network on Chip Switching With Graceful Performance Degradation-Reference-Cited by-同舟云学术

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Fault Tolerant Network on Chip Switching With Graceful Performance Degradation

Published:2010-06 Issue:6 Volume:29 Page:883-896
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Kohler Adán,Schley Gert,Radetzki Martin

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/5467322/05467330.pdf?arnumber=5467330

Cited by 51 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Introduction;Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design;2023

2. Congestion aware low power on chip protocols with network on chip with cloud security;Journal of Cloud Computing;2022-09-09

3. Deflection-Aware Routing Algorithm in Network on Chip against Soft Errors and Crosstalk Faults;2021 IEEE International Conference on Networking, Architecture and Storage (NAS);2021-10

4. Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router;2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS);2021-06-28

5. Evolution of Publications, Subjects, and Co-Authorships in Network-on-Chip Research From a Complex Network Perspective;IEEE Access;2021

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