Logic BIST With Capture-Per-Clock Hybrid Test Points-Reference-Cited by-同舟云学术

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Logic BIST With Capture-Per-Clock Hybrid Test Points

Published:2019-06 Issue:6 Volume:38 Page:1028-1041
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Moghaddam Elham^ORCID,Mukherjee Nilanjan,Rajski Janusz,Solecki Jedrzej,Tyszer Jerzy^ORCID,Zawada Justyna

Funder

Polish Ministry of Science and Higher Education

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx7/43/8718432/08355918.pdf?arnumber=8355918

Cited by 26 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Hybrid Test Point Insertion Strategy for Improved Test Metrics;2024 IEEE 8th International Test Conference India (ITC India);2024-07-21

2. A New Framework for RTL Test Points Insertion Facilitating a “Shift-Left DFT” Strategy;2023 IEEE International Test Conference (ITC);2023-10-07

3. A Test Point Selection Method Based on Fault Response Matrices Framework;IEEE Transactions on Instrumentation and Measurement;2023

4. Design of programmable memory BIST using stochastic sobol sequence pattern generator;AIP Conference Proceedings;2023

5. Hybrid non scan with built-in self-test for fault coverage improvement;5TH INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONIC, COMMUNICATION AND CONTROL ENGINEERING (ICEECC 2021);2023

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