A Test Point Selection Method Based on Fault Response Matrices Framework
Author:
Affiliation:
1. Electronic Engineering College, Heilongjiang University, Harbin, China
2. SWJTU-LEEDS Joint School, Southwest Jiaotong University, Chengdu, China
Funder
National Natural Science Foundation of China
Heilongjiang Provincial Key Laboratory of Micro-Nano Sensitive Devices and Systems
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Instrumentation
Link
http://xplorestaging.ieee.org/ielx7/19/10012124/10113339.pdf?arnumber=10113339
Reference34 articles.
1. Test Point Insertion with Control Point by Greater Use of Existing Functional Flip-Flops
2. Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops
3. Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs
4. Low cost test point insertion without using extra registers for high performance design
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