Hybrid non scan with built-in self-test for fault coverage improvement
Author:
Publisher
AIP Publishing
Link
http://aip.scitation.org/doi/pdf/10.1063/5.0120960
Reference16 articles.
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3. S. Ohtake, H. Wada, T. Masuzawa, and H. Fujiwara, “A non scan DFT method at register-transfer level to achieve complete fault efficiency,” Proceedings of the 2000 conference on Asia South Pacific Design Automation, (2000).
4. New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency
5. Logic BIST With Capture-Per-Clock Hybrid Test Points
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