Author:
Hameed Fazal,Bauer Lars,Henkel Jorg
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Cited by
12 articles.
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2. A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-01
3. PV-aware Replacement Policy for Two-level Shared Cache;2022 IEEE International Symposium on Smart Electronic Systems (iSES);2022-12
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5. Improving the Performance of Block-based DRAM Caches Via Tag-Data Decoupling;IEEE Transactions on Computers;2021-11-01