Author:
Qiu Xiang,Marek-Sadowska Malgorzata
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Cited by
6 articles.
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1. Implement a PnR Flow to Boost the Pin Density in Block Level Chip Design;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28
2. Morphed Standard Cell Layouts for Pin Length Reduction;2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2019-07
3. Efficiently Mapping VLSI Circuits With Simple Cells;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2019-04
4. A New Wire Optimization Approach for Power Reduction in Advanced Technology Nodes;Advances in Science, Technology and Engineering Systems Journal;2019
5. ISPD 2018 Initial Detailed Routing Contest and Benchmarks;Proceedings of the 2018 International Symposium on Physical Design;2018-03-25