Morphed Standard Cell Layouts for Pin Length Reduction
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8826391/8839309/08839520.pdf?arnumber=8839520
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node;IEEE Access;2024
2. Improving Pin Accessibility of Standard Cells under Power/Ground Stripes;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26
3. A Study on Optimizing Pin Accessibility of Standard Cells in the Post-3 nm Node;ACM/IEEE International Symposium on Low Power Electronics and Design;2022-08
4. Improving Pin Accessibility of Standard Cell Libraries in 7nm Technology;2022 23rd International Symposium on Quality Electronic Design (ISQED);2022-04-06
5. Six-track Standard Cell Libraries with Fin Depopulation, Contact over Active Gate, and Narrower Diffusion Break in 7nm Technology;2021 22nd International Symposium on Quality Electronic Design (ISQED);2021-04-07
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