Six-track Standard Cell Libraries with Fin Depopulation, Contact over Active Gate, and Narrower Diffusion Break in 7nm Technology
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9424228/9424248/09424315.pdf?arnumber=9424315
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Improvement of Mixed Track - Height Standard-Cell Placement;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25
2. Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-02
3. Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis;ACM/IEEE International Symposium on Low Power Electronics and Design;2022-08
4. Improving Pin Accessibility of Standard Cells Through Fin Depopulation;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28
5. Improving Pin Accessibility of Standard Cell Libraries in 7nm Technology;2022 23rd International Symposium on Quality Electronic Design (ISQED);2022-04-06
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