ISPD 2018 Initial Detailed Routing Contest and Benchmarks
Author:
Affiliation:
1. Cadence Design Systems, San Jose, CA, USA
2. Cadence Design Systems, Austin, TX, USA
Funder
Wen-Hao Liu
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3177540.3177562
Reference20 articles.
1. ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement
2. Routing congestion estimation with real design constraints
3. Case study for placement solutions in ispd11 and dac12 routability-driven placement contests
4. D. Shi etal Dynamic planning of local congestion from varying-size vias for global routing layer assignment. In IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD'17) Vol. 36 No. 8 2017. D. Shi et al. Dynamic planning of local congestion from varying-size vias for global routing layer assignment. In IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD'17) Vol. 36 No. 8 2017.
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