Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning-Reference-Cited by-同舟云学术

Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning

Published:2018-02 Issue:2 Volume:37 Page:392-405
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Zhang Grace Li,Li Bing^ORCID,Liu Jinglan,Shi Yiyu,Schlichtmann Ulf^ORCID

Funder

German Research Foundation (DFG)

Transregional Collaborative Research Centre “Invasive Computing” (SFB/TR 89)

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

2. A High-Performance Parallel Hardware Architecture of SHA-256 Hash in ASIC;2020 22nd International Conference on Advanced Communication Technology (ICACT);2020-02

4. A Configurable Approximation Min-Sum Decoding Algorithm for Low Density Parity Check Codes;Proceedings of the 9th International Conference on Information Communication and Management;2019-08-23

5. A Modified Method for General LDPC Bit-flipping Decoding;Proceedings of the 2019 7th International Conference on Computer and Communications Management;2019-07-27