A High-Performance Parallel Hardware Architecture of SHA-256 Hash in ASIC

Author:

Wu Ruizhen,Zhang Xiaoyong,Wang Mingming,Wang Lin

Publisher

IEEE

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Custom ASIC Design for SHA-256 Using Open-Source Tools;Computers;2023-12-25

2. Parallel Implementation of SHA256 on Multizone Heterogeneous Systems;2023 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom);2023-12-21

3. Implementation of a Hash-based Secure Core for Integrity and Authentication of Data in Space Applications on Space-grade FPGAs;2023 IEEE 2nd Industrial Electronics Society Annual On-Line Conference (ONCON);2023-12-08

4. Hardware Accelerated Reusable Merkle Tree Generation for Bitcoin Blockchain Headers;IEEE Computer Architecture Letters;2023-07

5. FPGA-based Implementation of SHA-256 with Improvement of Throughput using Unfolding Transformation;Pertanika Journal of Science and Technology;2022-01-10

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