A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs)-Reference-Cited by-同舟云学术

A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs)

Published:2019-06 Issue:6 Volume:38 Page:1109-1122
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Cao Xuebing^ORCID,Xiao Liyi^ORCID,Li Jie,Zhang Rongsheng^ORCID,Liu Shanshan^ORCID,Wang Jinxiang^ORCID

Funder

Fundamental Research Funds for the Central Universities

Harbin Institute of Technology

Harbin Science and Innovation Research Special Fund

Special Fund for Development of Shenzhen Strategic Emerging Industries

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. SEU/SET Evaluation of Digital VLSI Design from Register Transfer Level to Layout Level;2023 7th International Conference on Electrical, Mechanical and Computer Engineering (ICEMCE);2023-10-20

3. Addressing Single-Event-Multiple-Transient Faults in Asynchronous RH-Click Controllers;2023 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2023-08-28