FPGA-Based Cross-Hardware MBU Emulation Platform for Layout-Level Digital VLSI
Author:
Affiliation:
1. College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics,Nanjing,China
Funder
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10317938/10317940/10317974.pdf?arnumber=10317974
Reference18 articles.
1. Multiple Transient Faults in Combinational and Sequential Circuits: A Systematic Approach
2. Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs)
3. A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs)
4. Layout-Based Modeling and Mitigation of Multiple Event Transients
5. Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection
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