Stress sensitivity analysis on TSV structure of wafer-on-a-wafer (WOW) by the finite element method (FEM)
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/5069981/5090321/05090354.pdf?arnumber=5090354
Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI);Electronics;2022-01-12
2. Review of wafer-level three-dimensional integration (3DI) using bumpless interconnects for tera-scale generation;IEICE Electronics Express;2015
3. Interval optimal design of 3-D TSV stacked chips package reliability by using the genetic algorithm method;Microelectronics Reliability;2014-12
4. Impact of back-grinding-induced damage on Si wafer thinning for three-dimensional integration;Japanese Journal of Applied Physics;2014-04-23
5. Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art;Journal of Electronic Packaging;2014-02-18
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