A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects-Reference-Cited by-同舟云学术

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A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects

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Container-title:Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519)
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Author:

Lu J.-Q.,Kwon Y.,Rajagopalan G.,Gupta M.,McMahon J.,Lee K.-W.,Kraft R.P.,McDonald J.F.,Cale T.S.,Gutmann R.J.,Xu B.,Eisenbraun E.,Castracane J.,Kaloyeros A.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/7918/21830/01014893.pdf?arnumber=1014893

Cited by 24 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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3. A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2010-06

4. Silicon - Post Processing CMOS Wafers to Create Integrated Sensors, Mems and Electro-Optic Systems;SAIEE Africa Research Journal;2010-03

5. A Cost Comparison of VLSI Integration Schemes;3-Dimensional VLSI;2010

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