A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration-Reference-Cited by-同舟云学术

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A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration

Published:2010-06 Issue:6 Volume:18 Page:967-977
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Zia Aamir,Jacob Philip,Kim Jin-Woo,Chu Michael,Kraft Russell P.,McDonald John F.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/5471724/05223675.pdf?arnumber=5223675

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Evaluation of the Memory Communication Traffic in a Hierarchical Cache Model for Massively-Manycore Processors;2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP);2016-02

2. Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-09

3. A Modular Shared L2 Memory Design for 3-D Integration;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-08

4. Thermal Modeling of 3-D Stacked DRAM Over SiGe HBT BiCMOS CPU;IEEE Access;2015

5. Design of BiCMOS SRAMs for high‐speed SiGe applications;IET Circuits, Devices & Systems;2014-11

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