Gate architecture design for enhancement mode p-GaN gate HEMTs for 200 and 650V applications-Reference-Cited by-同舟云学术

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Gate architecture design for enhancement mode p-GaN gate HEMTs for 200 and 650V applications

Published:2018-05 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)
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Author:

Posthuma N. E.,You S.,Stoffels S.,Liang H.,Zhao M.,Decoutere S.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8387225/8393579/08393634.pdf?arnumber=8393634

Cited by 28 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 1.2 kV Enhancement-Mode p-GaN Gate HEMTs on 200 mm Engineered Substrates;IEEE Electron Device Letters;2024-04

2. Comparative Investigation on the Repetitive Short-Circuit Capability of 100 V Commercial p-GaN Gate Power HEMTs With Different Processing and Structure;IEEE Transactions on Electron Devices;2024-04

3. Stable High Temperature Operation of p-GaN Gate HEMT With Etch-Stop Layer;IEEE Electron Device Letters;2024-03

4. High-Voltage E-Mode p-GaN Gate HEMT on Sapphire With Gate Termination Extension;IEEE Transactions on Electron Devices;2024-03

5. Route Toward Commercially Manufacturable Vertical GaN Devices;IEEE Transactions on Electron Devices;2024

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