Aggressive Design Reuse for Ubiquitous Zero-Trust Edge Security—From Physical Design to Machine-Learning-Based Hardware Patching
Author:
Affiliation:
1. ECE Department, National University of Singapore, Queenstown, Singapore
Funder
Singapore National Research Foundation and the Cyber Security Agency through the “SOCure” Project
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/8782712/10019316/09955388.pdf?arnumber=9955388
Reference117 articles.
1. A PVT-Tolerant Oscillation-Collapse-Based True Random Number Generator With an Odd Number of Inverter Stages
2. A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement
3. A Feedback Architecture of High Speed True Random Number Generator based on Ring Oscillator
4. A New Energy-Efficient and High Throughput Two-Phase Multi-Bit per Cycle Ring Oscillator-Based True Random Number Generator
5. Fully Synthesizable Unified True Random Number Generator and Cryptographic Core
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring Static Inverter Selection and Noise Enhancement;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023
2. Opening of the 2023 Editorial Year—This Coda as Prelude of Next TVLSI Cycle With Sustained Growth;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-01
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