A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring Static Inverter Selection and Noise Enhancement-Reference-Cited by-同舟云学术

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A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring Static Inverter Selection and Noise Enhancement

Published:2023 Issue: Volume: Page:1-9
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Wang Xingyu¹^ORCID,Zhang Ruilin²^ORCID,Liu Kunyang¹^ORCID,Shinohara Hirofumi³^ORCID

Affiliation:

1. Production and Systems, Graduate School of Information, Waseda University, Kitakyushu, Japan

2. Production and Systems, Research Center of Information, Waseda University, Kitakyushu, Japan

3. Production and Systems, Graduate School of Information and the Research Center of Information, Waseda University, Kitakyushu, Japan

Funder

ROHM Company Ltd.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/4359553/10313118.pdf?arnumber=10313118

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. De-Correlation and De-Bias Post-Processing Circuits for True Random Number Generator;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

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