A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement
Author:
Affiliation:
1. Graduate School of Information, Production and Systems, Waseda University,Kitakyushu,Japan
Funder
Kitakyushu Foundation for the Advancement of Industry, Science and Technology (FAIS)
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9768045/9768046/09768078.pdf?arnumber=9768078
Reference12 articles.
1. 36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security
2. A 82-nW Chaotic Map True Random Number Generator Based on a Sub-Ranging SAR ADC
3. Energy-Efficient Post-Processing Technique Having High Extraction Efficiency for True Random Number Generators
4. An Accurate Probabilistic Reliability Model for Silicon PUFs;roel;CHES,2013
5. National Institute of Standards and Technologies;SP 800-22,2010
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