Mixed Logic Style Decoders for Low Power High Speed Applications
Author:
Affiliation:
1. Pilvi Systems Inc, Plano, Texas,Vellore,India
2. School of Electronics and Engineering, Vellore Institute of Technology,Vellore,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10156870/10156895/10156972.pdf?arnumber=10156972
Reference15 articles.
1. A differential binary message-passing LDPC decoder
2. Design and Implementation of Low Power – High Performance Mixed Logic Line Decoders;sahana;2019 4th International Conference on Recent Trends on Electronics Information Communication and Technology (RTEICT-2019),2019
3. Design of Low-Power High-Performance 2–4 and 4–16 Mixed-Logic Line Decoders
4. Modified Mixed logic design of 2:4 decoder;arya;Proceedings of the Fourth International Conference on Communication and Electronics Systems (ICCES 2019),0
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