Design of Low-Power High-Performance 2–4 and 4–16 Mixed-Logic Line Decoders

Author:

Balobas Dimitrios,Konofaos NikosORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 21 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. High-performance and low-power decoder circuits for SRAMs using mixed-logic scheme;Integration;2024-09

2. Ultra-low-power one-hot transmission-gate multiplexer (OTG-MUX) scalable into large fan-in circuits in 28 nm CMOS;Integration;2024-01

3. Highly Secure Approximate Adiabatic Logic for Error Tolerant Applications;2023 3rd International Conference on Pervasive Computing and Social Networking (ICPCSN);2023-06

4. Mixed Logic Style Decoders for Low Power High Speed Applications;2023 2nd International Conference on Vision Towards Emerging Trends in Communication and Networking Technologies (ViTECoN);2023-05-05

5. Design of Low power and High-Performance Decoder Using Carbon Nanotube Field Effect Transistor (CNTFET);2023 IEEE Devices for Integrated Circuit (DevIC);2023-04-07

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