1. A 1-nW ultra-low voltage subthreshold CMOS voltage reference with 0.0154%/V line sensitivity;Lin;IEEE Trans. Circuits Syst. II Exp. Briefs,2019
2. A 55 nm, 0.4V 5526-TOPS/W compute-in-memory binarized CNN accelerator for AIoT applications;Zhang;IEEE Trans. Circuits Syst. II Exp. Briefs,2021
3. A new low-power dynamic-GDI full adder in CNFET technology;Ghorbani;Integration,2022
4. Designing efficient FPGA tiles for power-constrained ultra-low-power applications;Razzaq;Integration,2021
5. 14.1 A 510nW 0.41V low-memory low-computation keyword-spotting chip using serial FFT-based MFCC and binarized depthwise separable convolutional neural network in 28 nm CMOS;Shan,2020