GDI Logic Based Design of Decoder Circuit for Low Power Applications
Author:
Affiliation:
1. RV College of Engineering,Electronics and Communication Engineering,Bangalore,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10333972/10333315/10334197.pdf?arnumber=10334197
Reference15 articles.
1. Low Power Self-Controlled Pre-Charge Free Content Addressable Memory
2. Memory Design and Verification of SRAM-based Energy Efficient Ternary Content Addressable Memory
3. Novel design technique of address Decoder for SRAM
4. A review on Buffer Chips and growing Memory Bandwidths;manoj;2022 International Journal for Research in Applied Science & Engineering Technology (IJRASET),0
5. VTEAM model based in-memory computation using memristors;chinmay;Ternational Journal of Innovative Technology and Exploring Engineering,2019
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1. Design and Performance Analysis of an Asynchronous 16×2 DRAM Architecture Using 2T1C DRAM Bitcell and 70.15 µW GDI Based 2 to 4 Decoder;2024 6th International Conference on Electrical Engineering and Information & Communication Technology (ICEEICT);2024-05-02
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