A 5.3-fJ/conv.-step Pipelined-SAR ADC with Resistance Assisted Two-Stage Dynamic Amplifier Based on Gm-Unit-Reference-Cited by-同舟云学术

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A 5.3-fJ/conv.-step Pipelined-SAR ADC with Resistance Assisted Two-Stage Dynamic Amplifier Based on Gm-Unit

Published:2023-10-20 Issue: Volume: Page:
ISSN:
Container-title:2023 8th International Conference on Integrated Circuits and Microsystems (ICICM)
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Author:

Su Qing¹,Li Dawei²,Guo Xuan³,Zhang Heng¹,He Ben¹,Jia Hanbo³,Wu Danyu³,Liu Xinyu³

Affiliation:

1. Institute of Microelectronics of the Chinese Academy of Sciences, University of Chinese Academy of Sciences,Beijing,China

2. University of Chinese Academy of Sciences,Beijing,China

3. Institute of Microelectronics of the Chinese Academy of Sciences,Beijing,China

Funder

Chinese Academy of Sciences

Youth Innovation Promotion Association

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10365709/10365561/10365869.pdf?arnumber=10365869

Reference9 articles.

1. 28.4 A 12b 330MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving <1dB SNDR variation

2. A 0.004mm² 200MS/S Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp

3. 27.4 A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier

4. A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier

5. High CMRR Voltage Mode Instrumentation Amplifier Using a New CMOS Differential Difference Current Conveyor Realization

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